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AX88780 asix electronics corporatio n released date: 5/18/2007 4f, no.8, hsin ann rd., science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http://www.asix.com.tw high-performance non-pci single-chip 32-bit 10/100m fast ethernet controller document no: AX88780/v1.4 features high-performance n on-pci local bus 16/32-bit sram- like host interface support big/little endian data bus type large embedded sram for packet buffers 32k bytes for receive buffer 8k bytes for transmit buffer support ip/tcp/udp checksum offloads support interrupt with high or low active trigger mode single-chip fast ethernet controller compatible with ieee802.3, 802.3u standards integrated fast ethernet mac/phy transceiver in one chip support 10mbps and 100mbps data rate support full and half duplex operations support 10/100mbps n-way auto-negotiation operation support ieee 802.3x flow control for full-duplex operation support back-pressure flow control for half-duplex operation support packet length set by software support mii interface for external ethernet phy and homepna/homeplug phy applications support wake-on-lan function by following events detection of network link-up state receipt of a magic packet support magic packet detection for remote wake-up after power?on reset support eeprom interface support pcmcia in 16-bit mode support synchronous or asynchronous mode to host mcu support led pins for various network activity indications integrated voltage regulator from 3.3v to 2.5v 2.5v for core and 3.3v i/o with 5v tolerance 128-pin lqfp with cmos process, rohs package us patent approved (no 6799231) product description the AX88780 is a high-perform ance and cost-effective single-chip fast et hernet controller for various embedded systems including consumer electronics and home network markets that require a higher level of network connectivity. the AX88780 supports 16/32-bit sram-like host interface and integrates on-chip fast ethernet mac and phy, which is ieee802.3 10base-t and ieee802.3u 100base-t compatib le. the AX88780 supports full-duplex or half-duplex operation at 10/100mbps speed with auto-negotiation or manual setting. the AX88780 integrates large embedded sram for packet buffers to accommodate high bandwidth applications and supports ip/tcp/udp checksum to offload processing loading from microprocessor/microcontroller in an embedded system. system block diagram always contact asix for possible updates before starting a design. this data sheet contains new produc ts information. asix electronics rese rves the rights to modify product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product.
AX88780 2 asix electronics corporation target applications multimedia applications content distribution application audio distribution system (whole-house audio) video-over ip solutions, ip pbx and video phone video distribution system, multi-room pvr cable, satellite, and ip set-top box digital video recorder dvd recorder/player high definition tv digital media client/server home gateway iptv for triple play others printer, kiosk, security system wireless router & access point applications
AX88780 3 asix electronics corporation content 1.0 introduction............................................................................................................... .......................................................... 7 1.1 general description ........................................................................................................ ............................................... 7 1.2 AX88780 bl ock diagram...................................................................................................... ......................................... 7 1.3 AX88780 pino ut diagram..................................................................................................... ......................................... 8 2.0 signal description......................................................................................................... ...................................................... 9 2.1 signal type definition ..................................................................................................... .............................................. 9 2.2 host interface............................................................................................................. .................................................... 9 2.3 eeprom interface ........................................................................................................... ........................................... 10 2.4 regulator interface........................................................................................................ ............................................... 11 2.5 10/100m phy interface ...................................................................................................... ......................................... 11 2.6 mii interface .............................................................................................................. .................................................. 11 2.7 miscellaneous .............................................................................................................. ................................................ 12 2.8 power/ground pin........................................................................................................... .............................................. 12 3.0 functional description..................................................................................................... ................................................. 13 3.1 host interface............................................................................................................. .................................................. 13 3.2 system ad dress range....................................................................................................... .......................................... 13 3.3 tx buffer operation ........................................................................................................ ............................................ 13 3.4 rx buffer operation........................................................................................................ ............................................ 13 3.5 flow control ............................................................................................................... ................................................. 14 3.6 checksum offloads and wake-up .............................................................................................. .................................. 14 3.7 fast-mode support .......................................................................................................... ............................................. 14 3.8 big/little-endi an support .................................................................................................. ........................................... 14 3.9 10/100base-tx phy.......................................................................................................... ....................................... 14 3.9 16-b it mo de................................................................................................................ .................................................. 15 3.11 eeprom format ............................................................................................................. .......................................... 16 4.0 register descrip tion ....................................................................................................... .................................................. 17 4.1 cmd--command register ...................................................................................................... ..................................... 18 4.2 imr--interrupt mask re gister ............................................................................................... ...................................... 18 4.3 isr--interrupt status register............................................................................................. ......................................... 19 4.4 tx_cfg--tx configuration register .......................................................................................... ............................... 20 4.5 tx_cmd--tx command register ................................................................................................ ............................. 20 4.6 txbs--tx buffer status register ............................................................................................ ................................... 20 4.7 phy_ctrl-- internal phy contro l regi ster ................................................................................... .......................... 21 4.8 txdes0--tx descriptor0 register............................................................................................ ................................. 22 4.9 txdes1--tx descriptor1 register............................................................................................ ................................. 22 4.10 txdes2--tx de scriptor2 register........................................................................................... ................................ 22
AX88780 4 asix electronics corporation 4.11 txdes3--tx descriptor3 register ........................................................................................... ................................ 23 4.12 rx_cfg--rx conf iguration register......................................................................................... .............................. 23 4.13 rxcurt--rx current pointer register ....................................................................................... ............................. 23 4.14 rxbound--rx bound ary pointer register ..................................................................................... ....................... 24 4.15 mac_cfg0--mac conf iguration0 register..................................................................................... ....................... 24 4.16 mac_cfg1--mac conf iguration1 register..................................................................................... ....................... 24 4.17 mac_cfg2--mac conf iguration2 register..................................................................................... ....................... 25 4.18 mac_cfg3--mac conf iguration3 register..................................................................................... ....................... 25 4.19 txpaut--tx pause time register ............................................................................................ ............................... 25 4.20 rxbthd0--rx buffer threshold0 register .................................................................................... ......................... 25 4.21 rxbthd1--rx buffer threshold1 register .................................................................................... ........................ 26 4.22 rxfulthd--rx buffer full threshold register............................................................................... ...................... 26 4.23 misc?misc. control re gister ............................................................................................... .................................. 26 4.24 macid0--mac id0 re gister .................................................................................................. ................................. 27 4.25 macid1--mac id1 re gister .................................................................................................. ................................. 27 4.26 macid2--mac id2 re gister .................................................................................................. ................................. 27 4.27 txlen--tx length register ................................................................................................. ................................... 27 4.28 rxfilter--rx pack et filter register ....................................................................................... .............................. 27 4.29 mdioctrl--mdio control re gister ........................................................................................... ........................... 28 4.30 mdiodp--mdio da ta port register ........................................................................................... ............................. 28 4.31 gpio_ctrl--gpi o control register.......................................................................................... ............................. 29 4.32 rxindicator--receiv e indicator register................................................................................... ......................... 29 4.33 txst--tx status register .................................................................................................. ....................................... 29 4.34 mdclkpat--mdc cl ock pattern regist er ...................................................................................... ........................ 30 4.35 rxchksumcnt--rx ip/udp /tcp checksum error counter......................................................................... ...... 30 4.36 rxcrcnt--rx crc error counter............................................................................................. ............................ 30 4.37 txfailcnt--tx fail counter ................................................................................................ ................................. 30 4.38 promdpr--eeprom data port register ........................................................................................ ....................... 30 4.39 promctrl--eepro m control register ......................................................................................... ....................... 31 4.40 maxrxlen--max. rx packet lengt h register.................................................................................. .................... 31 4.41 hashtab0--hash table0 register ............................................................................................ .............................. 31 4.42 hashtab1--hash table1 register ............................................................................................ .............................. 32 4.43 hashtab2--hash table2 register ............................................................................................ .............................. 32 4.44 hashtab3--hash table3 register ............................................................................................ .............................. 32 4.45 dogthd0?watch dog ti mer threshold0 register ............................................................................... ................ 32 4.46 dogthd1?watch dog ti mer threshold1 register ............................................................................... ................. 32 4.47 softrst ? softwa re reset register......................................................................................... ................................. 33 5.0 phy register ............................................................................................................... ..................................................... 34
AX88780 5 asix electronics corporation 5.1 bmcr--basic mode control register.......................................................................................... ............................... 34 5.2 bmsr--basic mode status register........................................................................................... ................................. 35 5.3 phyidr0--phy id entifier 0 register ......................................................................................... ................................ 35 5.4 phyidr1--phy id entifier 1 register ......................................................................................... ................................ 36 5.5 anar--auto-negotiation advertisemen t register .............................................................................. ........................ 36 5.6 anlpar--auto-negotiation li nk partner ab ility regi ster ..................................................................... .................... 36 5.7 aner--auto-negotiati on expansion regist er .................................................................................. ........................... 37 6.0 electrical specifi cation and timings ....................................................................................... ......................................... 38 6.1 dc charac teris tics ......................................................................................................... .............................................. 38 6.1.1 absolute maximum ratings ............................................................................................................ 38 6.1.2 general operation conditions ........................................................................................................ 38 6.1.3 leakage current and capacitance ................................................................................................... 38 6.1.4 dc characteristics of 2.5v io pins .................................................................................................. 38 6.1.5 dc characteristics of 3.3v io pins .................................................................................................. 39 6.1.6 transmission characteristics .......................................................................................................... 39 6.1.7 reception characteristics .............................................................................................................. 39 6.1.8 power consumption ...................................................................................................................... 40 6.1.9 thermal characteristics ................................................................................................................ 41 6.2 a.c. timing characteristics ................................................................................................ ......................................... 41 6.2.1 host clock ............................................................................................................................... ... 41 6.2.2 reset timing ............................................................................................................................... . 41 6.2.3 host single write timing ................................................................................................................ 42 6.2.4 host burst write timing ................................................................................................................. 43 6.2.5 host single read timing ................................................................................................................ 43 6.2.6 host burst read timing ................................................................................................................. 44 6.2.7 mii receive timing (100mb/s) ........................................................................................................ 44 6.2.8 mii transmit timing (100mbps) ...................................................................................................... 45 6.2.9 mdio timing .............................................................................................................................. 45 6.2.10 serial eeprom timing ............................................................................................................... 46 7.0 package information ........................................................................................................ ................................................. 47 8.0 ordering information....................................................................................................... ................................................. 48 appendix a1. 16-bit mode addres s and data bus............................................................................................... ................ 49 appendix a2. 32-bit mode addres s and data bus............................................................................................... ................ 51 appendix a3. synchronous and asynchro nous timing selection.................................................................................. ..... 52 appendix a4. wake on lan (wol) without driver via ma gic packet........................................................................... 53 revision history ............................................................................................................... ...................................................... 54
AX88780 6 asix electronics corporation list of figures figure 1: AX88780 block diagram ................................................................................................ ....................................... 7 figure 2: AX88780 pi n connection diagram....................................................................................... .................................. 8 figure 3: 32-bit m ode address mapping.......................................................................................... ...................................... 13 figure 4: data swap block ...................................................................................................... ............................................... 14 figure 5: 16-bit m ode address mapping.......................................................................................... ...................................... 15 figure 6: transmit wa veform speci fication ...................................................................................... .................................... 39 list of tables table 1 : host inte rface signal s group ......................................................................................... ............................................. 9 table 2: eeprom inte rface signals group........................................................................................ ..................................... 10 table 3: regulato r signals group ............................................................................................... ............................................. 11 table 4: 10/100m twiste d-pair signals group.................................................................................... ..................................... 11 table 5: mii interf ace signals group........................................................................................... ............................................ 11 table 6: miscellane ous signal s group ........................................................................................... .......................................... 12 table 7: power/gr ound pins group ............................................................................................... .......................................... 12 table 8: mac re gister mapping.................................................................................................. .......................................... 17 table 9 : phy re gister mapping ................................................................................................. ........................................... 34
AX88780 7 asix electronics corporation 1.0 introduction 1.1 general description AX88780 supports full-duplex or half-dup lex operation at 10/100 mbps speed with auto-negotiation or manual setting. the AX88780 has two built-in synchronous srams for buffer ing packet. the one is 32k bytes for receiving packets from ethernet; the other is 8k-bytes for transmitting packets from host system to ethernet. the AX88780 also has 256 bytes built-in configuration regi sters. for software programming, the total address space used in ax 88780 is 64k bytes in 32-bit mode and at least (8k + 8) bytes in 16-bit mode. because AX88780 is a sram-like device, AX88780 could be treated as a sram device and be attached to sram controller of system. therefore, system can execute dma cycles to gain the highe st performance. AX88780 needs 2 clock sources, one is hclk and another one is xtlp. the hclk clock can be from the host system clock or from a stand-along osc, and the xtlp/xtln clock is 25mhz for internal phy. 1.2 AX88780 block diagram figure 1: AX88780 block diagram
AX88780 8 asix electronics corporation 1.3 AX88780 pinout diagram the AX88780 is housed in the 128-pin lqfp package. figure 2: AX88780 pin connection diagram gnda 87 rxdv 70 ha15 21 mdio 59 v25out 38 hd0 19 vcc25 60 rxd3 77 vcc33 119 AX88780 vcc25a 85 hd12 5 gndr 36 intn 102 rxd1 75 hd17 126 hd30 109 gnda 82 mdc 58 hd13 3 txd0 65 hd2 17 hd19 124 ha12 24 vcc25 107 xtln 90 col 80 ha2 41 txon 93 txd1 63 txd3 61 ibref_wesd 88 ha14 22 oen 43 hd6 12 gnda 95 ha8 29 vcc25 27 hd27 112 nc 68 na 51 phyintn 46 vcc25 117 ha6 31 hd29 110 hclk 104 eedi 49 hd8 10 rxd0 74 ha3 34 vcc25a 100 wen 44 hd4 15 gnd 56 gnd 73 gnd 8 ha5 32 vcc25a 98 hd20 122 vcc33 105 spdled 54 non-pci 16/32-bit 10/100m fast ethernet controller with embedded phy rxclk 71 ha7 30 vcc25 78 vcc33 13 hd22 120 gnda 86 vcc25 20 hd11 6 vcc33r 37 rst_n 103 hd16 127 rxd2 76 rxin 83 txen 66 rxip 84 vcc25 4 reg_en 39 hd1 18 gnda 101 vcc33 1 hd18 125 ha11 25 AX88780 hd31 108 xtlp 91 vcc25a 81 vcc25 57 ha1 42 ha13 23 vcc25 123 vcc25 64 gnd 106 vcc25a 89 crs 79 vcc33 40 wakeup 115 vcc25a 96 txd2 62 hd26 113 txclk 69 test0 52 eeclk 47 txop 94 hd7 11 hd15 128 ha9 28 hd23 118 hd28 111 nc 67 eedo 50 csn 45 eecs 48 hd24 116 hd25 114 ha10 26 gnda 92 hd3 16 hd9 9 ha4 33 gnda 99 linkled 55 vcc25 72 hd5 14 hd10 7 hd14 2 rstpb 97 vcc25 35 hd21 121 test1 53
AX88780 9 asix electronics corporation 2.0 signal description 2.1 signal type definition i3: input, 3.3v with 5v tolerance i2: input, 2.5v with 3.3v tolerance i25 input, 2.5v only o3: output, 3.3v o2: output, 2.5v io3: input/output, input 3.3v with 5v tolerance io2 input/output, input 2.5v with 3.3v tolerance tso: tri-state output od: open drain allows multiple devices to share as a wire-or pd: internal 75k pull down pu: internal 75k pull up gnd: ground vcc3: 3.3v power vcc2: 2.5v power i: input only o: output only io: input/output 2.2 host interface table 1 : host interface signals group pin name type pin no pin description intn tso, 8ma 102 interrupt to host system when the polarity is active high, this signal must be pulled low, otherwise pulled high in active low environment. software set the bit6 of command register (cmd) to response the polarity. rst_n i3 103 reset signal: active low. hclk i3 104 reference clock. this clock may be from host (synchronous mode) or the output of stand-alone osc (asynchronous mode). wakeup tso, 8ma 115 wake-up signal to system. when the polarity of system is active high, this signal must be pulled low, otherwise pulled high in active low environment. software set the bit0 of command register (cmd) to response the polarity. hd0 io3, 8ma 19 data bus bit0. hd1 io3, 8ma 18 data bus bit1. hd2 io3, 8ma 17 data bus bit2. hd3 io3, 8ma 16 data bus bit3. hd4 io3, 8ma 15 data bus bit4. hd5 io3, 8ma 14 data bus bit5. hd6 io3, 8ma 12 data bus bit6. hd7 io3, 8ma 11 data bus bit7. hd8 io3, 8ma 10 data bus bit8. hd9 io3, 8ma 9 data bus bit9. hd10 io3, 8ma 7 data bus bit10. hd11 io3, 8ma 6 data bus bit11. hd12 io3, 8ma 5 data bus bit12. hd13 io3, 8ma 3 data bus bit13. hd14 io3, 8ma 2 data bus bit14. hd15 io3, 8ma 128 data bus bit15. hd16 io3, 8ma 127 data bus bit16, internal pull down. * hd17 io3, 8ma 126 data bus bit17, internal pull down. * hd18 io3, 8ma 125 data bus bit18, internal pull down. *
AX88780 10 asix electronics corporation hd19 io3, 8ma 124 data bus bit19, internal pull down. * hd20 io3, 8ma 122 data bus bit20, internal pull down. * hd21 io3, 8ma 121 data bus bit21, internal pull down. * hd22 io3, 8ma 120 data bus bit22, internal pull down. * hd23 io3, 8ma 118 data bus bit23, internal pull down. * hd24 io3, 8ma 116 data bus bit24, internal pull down. * hd25 io3, 8ma 114 data bus bit25, internal pull down. * hd26 io3, 8ma 113 data bus bit26, internal pull down. * hd27 io3, 8ma 112 data bus bit27, internal pull down. * hd28 io3, 8ma 111 data bus bit28, internal pull down. * hd29 io3, 8ma 110 data bus bit29, internal pull down. * hd30 io3, 8ma 109 data bus bit30, internal pull down. * hd31 io3, 8ma 108 data bus bit31, internal pull down. * ha1 i3 42 address bus bit1. ha2 i3 41 address bus bit2. ha3 i3 34 address bus bit3. ha4 i3 33 address bus bit4. ha5 i3 32 address bus bit5. ha6 i3 31 address bus bit6. ha7 i3 30 address bus bit7. ha8 i3 29 address bus bit8. ha9 i3 28 address bus bit9. ha10 i3 26 address bus bit10. ha11 i3 25 address bus bit11. ha12 i3 24 address bus bit12. ha13 i3 23 address bus bit13. ha14 i3 22 address bus bit14. ha15 i3 21 address bus bit15. wen i3 44 data write enable host drives wen and it is active low. csn i3 45 chip select enable host drives csn and it is active low. oen i3 43 data output enable host drives oen and it is active low. *note: the internal pull-down of hd16 to hd31 will be disabled in 32-bit mode. 2.3 eeprom interface table 2: eeprom interface signals group pin name type pin no pin description eeclk o3, 12ma 47 a low speed clock to eeprom eecs o3, 12ma 48 chip select to eeprom device. this pin will be treated as full-duplex indicator when bit10 of phy_ctrl register is set to high. it is active high in full-duplex mode, and low in half-duplex mode. eedi o3, 12ma 49 data to eeprom, valid in eecs is high and eeclk in rising edge. this pin will be treated as collision indicat or when bit10 of phy_ctrl register is set to high. it is active high in collision indicator. eedo i3, pd 50 data from eeprom
AX88780 11 asix electronics corporation 2.4 regulator interface table 3: regulator signals group pin name type pin no. pin description vcc33r vcc3 37 3.3v power to internal regulator gndr gnd 36 ground pin for internal regulator reg_en i3 39 high to enable internal regulator. low to disable internal regulator. v25out o2 38 2.5v output from internal regulator, max 250ma, when reg_en pin is high. 2.5 10/100m phy interface table 4: 10/100m twisted-pair signals group pin name type pin no. pin description rxin i 83 differential received input signal for both 10base-t and 100bse-tx modes . (note: please refer to s ection 6.1.7 for detailed tr ansmission characteristics) rxip i 84 differential received input signal for both 10base-t and 100bse-tx modes. txon o 93 differential transmitted output si gnal for both 10base-t and 100base-tx modes. (note: please refer to s ection 6.1.6 for detailed reception characteristics) txop o 94 differential transmitted output si gnal for both 10base-t and 100base-tx modes 2.6 mii interface table 5: mii interface signals group pin name type pin no. pin description txen o2, 12ma 66 transmit enable: txen is transition synchronously with respect to the rising edge of txclk. txen indicates that the port is presenting nibbles on txd [3:0] for transmission. txd[3:0] o2, 12ma 61,62, 63,65 transmit data: txd[3:0] is transition synchronously with respect to the rising edge of txclk. txclk i2 69 transmit clock: txclk is a continuous clock from phy. it provides the timing reference for the transfer of the txen and txd[3:0] signals from the mii port of phy. rxclk i2 71 receive clock: rxclk is a continuous clock from phy. it provides the timing reference for the transfer of the rxdv, rxd[3:0] signals from mii port of phy. rxd[3:0] i2 77,76,75, 74 receive data: rxd[3:0] is driven by the phy sync hronously with respect to rxclk. rxdv i2 70 receive data valid: rxdv is driven by the phy synchronously with respect to rxclk. asserted high when valid data is present on rxd [3:0]. col i2 80 collision signal: this signal is driven by phy when collision is detected. crs i2 79 carrier sense: asynchronous signal crs is asserted by the phy when either the transmitted or receive medium is non-idle. mdio io2, 8ma,pu 59 station management data input /output: serial data input/output transfers from/to the phy. the transfer protocol conforms to the ieee 802.3u mii specification. mdc o2, 8ma 58 station management data clock: the timing reference for mdio. all data tr ansfers on mdio are synchronized to the rising edge of this clock. phyintn i2 46 an interrupt signal from phy, active low.
AX88780 12 asix electronics corporation 2.7 miscellaneous table 6: miscellaneous signals group pin name type pin no. pin description linkled io3, 12ma, pd 55 in power-on reset phase, this pin will be latched by AX88780 to determine that system operates in 32 or 16-bit mode. high state is 16-bit mode and low state is 32-bit mode. the default is in 32-bit mode. upon finishing reset status, if bit11 of phy_ctrl register is enabled, this pin stands for: link: indicates a good link status, active low in 16-bit mode and active high in 32-bit mode. the link indicator only works under bit11 of phy_ctrl register set by driver. traffic: indicates the traffic status an d flashes while in tx or rx state. spdled io3, 12ma, pd 54 in power-on reset phase, this pin will be latched by AX88780 to determine whether AX88780 swaps the data or not. if the hi gh state, AX88780 will swap the data (big-endian). the default is little-endian. upon finishing reset stage, if bit12 phy_ctrl register is enabled, this pin stands for speed mode. in little-endian mode, low indi cates that phy is in 10base-tx mode, and high state indicates phy is in 100base-t mode. in big-endian mode, low indicates that phy is in 100mbase-t mode and high state indicates phy is in 10base-tx mode. the speed indicator only works under bit12 of phy_ctrl register set by driver. na i3 51 this pin is tied to ground for normal operation. test0 i3, pd 52 pull down (by 4.7k) or floating for normal operation. test1 i3, pd 53 pull down (by 4.7k) or floating for normal operation. xtln i25 90 25mhz crystal or oscillator clock input. the recommended reference frequency is 25mhz +/- 0.005% (i.e. 25mhz +/- 1250hz). this input pin is only 2.5v tolerant and should not apply 3.3v clock signal directly to this pin if an external oscillator is used. xtlp o2 91 25mhz crystal clock output. for 25mhz oscillator clock, this pin should be kept floating. rstpb i25 97 pull-up for normal operation. ibref_wesd i25 88 connect a 12.3kohm resistor to ground. nc o 67,68 no connection 2.8 power/ground pin table 7: power/ground pins group pin name type pin no. pin description vcc33 vcc3 1,13,40, 105, 119 digital 3.3v power vcc25 vcc2 4,20,27,35,57,60,64,72,78,107,117,123 digital 2.5v power gnd gnd 8, 56, 73,106 digital ground vcc25a vcc2 81,85,89,96,98,100 2.5v power for phy analog par t gnda gnd 82,86,87,92,95,99,101 analog ground
AX88780 13 asix electronics corporation 3.0 functional description 3.1 host interface AX88780 supports a very simple sram-lik e interface. there are only 3 control si gnals to operate the read or write. for write operation, host activates csn and wen to low with address and data bus. AX88780 will decode and latched the data into internal buffer. for normal operation, the wen needs at least 4 clocks duration for one 32/16-bit write operation. the csn can always be driven, but wen must at least be de-asserted 1 clock before next access. for read operation, host asserts csn and oen at least 5 clocks to AX88780, the data will be valid after 4 clocks. AX88780 also support burst mode if host reads/writes AX88780 by continuous access. note: the burst mode only su pports in tx/rx, not su pports in register read/write. that is, read rx area from xxxx_0000 to xxxx_7fff or write tx area from xxxx_8000 to xxxx_fbff can be accessed by burst mechanism. 3.2 system address range AX88780 is suitable to attach to sram controller, so it needs 64k memory space to operate. the designer can allocate any block (64k) in system space. from offset 0x0000 to 0x7fff is fo r rx operation, and offset 0x8000 to 0xfbff is for tx operation. the internal configuration regi ster of AX88780 is allocated in offset 0xfc00 to 0xfcff. below is the mapping of addressing. figure 3: 32-bit mode address mapping 3.3 tx buffer operation AX88780 employs 4 descriptors to maintain transmit informat ion, such as packet length, start bit. these descriptors are located in offset 0xfc20, 0xfc24, 0xfc 28 and 0xfc2c. driver can choose any descriptor whenever there is data need to be transmitted. since there are only 4 descriptors, upon running out of descriptors, driver must wait for the descriptor is to be released by AX88780. 3.4 rx buffer operation AX88780 is built a 32k sram for rx operation. it utilizes ring structure to maintain the input data from phy and read out to host. there are two pointer registers located in offset 0xfc34 and 0xfc38. AX88780 will maintain rxcurt register. upon it receives a valid packet from phy it will update rxcurt accordin g to the packet length. driver reads data from AX88780 and maintains the rxbound register. when driver finishes reading packet, it must update rxbound according to the packet length. AX88780 utilizes rxcurt and rxbound to provide receive buffer status, full or empty. r x area 32768 bytes xxxx_ 0000h xxxx _8000h xxxx_fc00h 31 0 t x area 31744 bytes r egisters area 256 bytes xxxx_fd00h n o used area 768 bytes xxxx_ffffh
AX88780 14 asix electronics corporation 3.5 flow control in full duplex mode, AX88780 su pports the standard flow control mechanis m defined in ieee 802.3x standard. it enables the stopping of remote node tr ansmissions via a pause frame information interaction. when space of the packet buffer is less than the threshold values (rxbthd0, rxbthd 1), AX88780 will send out a pause-on packet to stop the remote node transmission. and then ax887 80 will send out a pause-off packet to inform the remote node to retransmit packet if it has enough space to receive packets. 3.6 checksum offloads and wake-up to reduce the computing loading of cpu, AX88780 is built checksum operator for ip, udp or tcp packet. AX88780 will detect the packet whether it is ip, udp or tcp packet. if it is an ip packet, AX88780 will calculate the checksum of header and put the result in checksum filed of ip. then it continuously checks the packet whether it is udp or tcp. it will perform the checksum operation whenever it is a udp or tcp packet. AX88780 also automatically skip the vlan tag when checksum is executed. AX88780 also supports to detect magic packet or lin k-up to wake up system when system is in sleep state or needs to cold start by magic packet. 3.7 fast-mode support to improve the throughput in embedde d system, AX88780 supports fast-mode for tx/rx buffer access. host can access AX88780 by driving csn to low and toggle wen (write) or oen (read). AX88780 can support the burst until whole packet access. the access timing can refer to section 6. 2.4 and 6.2.6. this mechanis m is only for tx/rx buffer access. for configuration register access, it must use single access. 3.8 big/little-endian support AX88780 supports ?big? or ?little? endian data format. the default is little-endian. designer can pull-up spdled pin to high to swap the data format. below table can depict the relation. this swap is only valid in 32-bit mode. figure 4: data swap block 3.9 10/100base-tx phy AX88780 integrates high performance phy that is fully compliant with 10/100base-tx ethernet standards such as ieee 802.3, ieee 802.3u and ansi x3.263-1995. it?s main features can described below. adaptive equalizer this equalizer mainly eliminates the distortions caused by inter-symbol interference (isi) by automatically adjusting the mathematical coefficient to match the cable length. baseline wander correct the transmitter sends dc and ac signals as a pair. th e receiving device and transmitting device each have a transformer that blocks the dc signal. when the ac signal loses its dc component, the ac signal becomes distorted. the baseline-wander correct ill restores the dc component to ac signal and delivers it as a complete signal to receiver. link monitor/signal detect this feature is used to detect the signal?s level. if th e detected signal is above 400mv in 100base-tx mode, it will generate a signal detected (sd) to mac. if the level is below 400mv, the sd signal will be de-asserted 1ms. carrier detect and 4b/5b coding the physical coding sub-layer (pcs) checks with physical medium attachment (pma) data to see if the packets meet ieee 802.3u defined preamble (j/k/p ackets in 100base-tx) standards. if th e packets meet the standards, the pcs sub-layer will start to process the data and send to mac engine. the pcs converts received/transmitted data according ieee 802.3u defined coding standards, such as 4b/5b and scrambling/de-scrambling. little-endian d[31:24] d[23:16] d[15:8] d[7:0] d[7:0] d[15:0] d[23:16] d[31:24] big-endian
AX88780 15 asix electronics corporation 3.9 16-bit mode AX88780 also supports 16-bit mode ope ration. AX88780 driver should request at least (8k + 8) bytes space for tx, rx and register access. for example, the dr iver requests a 16k bytes space from syst em and then sets the new window base address to membas6 register. after that, driver should set bit 0 (decode_en) of membase register to start decoding for tx buffer, rx buffer and registers access. (note: AX88780 h/w only decodes lo w 16-bit offset address.) membase--memory base address field name type default description 15:1 - r/w - reserved. the output value is undefined if software read this field. 0 decode_en r/w 0 16-bit decode enable set to ?1? to start decoding. membas6--memory base address + 6 field name type default description 15:8 - r/w - reserved. the output value is undefined if software read this field. 7:0 winsize r/w 0x00 window base pointer. (the msb of new window base address) this field defines another new windows base address for tx, rx and register access. the total size is 8k bytes. tx areas occupy 3840 bytes registers occupy 256 bytes. rx areas occupy 4096 bytes. note: the winsize field of this address is used to define the msb of new window base address, the tx buffer, rx buffer and registers should be accessed through this new window base address in 16-bit mode. please refer to below mapping mechanism for details. membase set membas6 = 0x0010 tx buffer area (3840 bytes) registers area (256 bytes) rx buffer area (4096 bytes) figure 5: 16-bit mode address mapping the following is an example to indicate how to define a new window base address in 16-bit mode by configuring the membas6 register. if AX88780 is allocated at the memory base address 0x20_0000 by hardware (i.e. the membase register is allocated at 0x20_0000) and users would like to set the new window base address to 0x20_1000, the driver should write 0x0010 to the membas6 register (offset 0x20_0006) . in this case, the tx buffer area will be allocated from 0x20_1000 to 0x20_1eff; the registers area will be allocated from 0x20_1f00 to 0x20_1fff and the rx buffer area will be allocated from 0x20_2000 to 0x20_2fff. 15 0 registers area (xx_1f00 ~ 1fff) rx buffer area (xx_2000 ~ 2fff) base address (xx_0000) base address + 6 (xx_0006) n ew window base address (xx_ 10 00) tx buffer area (xx_1000 ~ 1eff)
AX88780 16 asix electronics corporation 3.11 eeprom format AX88780 will auto-load data from eeprom device after hard ware reset. if the eeprom device is not attached, the loading operation will be discarded. the eeprom mainly prov ides mac address information and cis information if it is used in pcmcia environment. below table is the format if eeprom device is employed. no te: if the mac address is 12 34 56 78 9a bc (msb-lsb) then driver should set macid0=0x9abc, macid1=0x5678 and macid2=0x1234. address description 0 pointer to cis area starting address. set this field to 0x0070 to shorten the download eeprom if there is no cis needed. AX88780 only supports 93c56-16bit mode, thus the max value of this field is 0x007f. this field should not be set to 0x0000 or 0xffff; otherwise, AX88780 will not recognize the eeprom during hardware reset. 1 macid0 data 2 macid1 data 3 macid2 data 4 reserved, keep all 0?s 5 bit0: when linkled is set to ?1? in reset stage, this bit indicates AX88780 whether or not it is in the environment of pcmcia. 0 = general 16-bit mode, 1= special for pcmcia environment of 16-bit mode. bit1: 0 = use external phy, 1 = use internal phy. this function is independen t from phy_en bit of ph y_ctrl register. either of both is set will force AX88780 to select internal phy. others bit set to 0s for normal operation 6 ~ 11 reserved, keep all 0?s 12 ~ 127 cis area, if it used in pcmcia system, otherwise don?t care these fields
AX88780 17 asix electronics corporation 4.0 register description there are some registers located from of fset 0xfc00 to 0xfcff. all of the registers are 32-bit boundary alignment, but only low 16-bit are available (exception 0xfc54). for reserved bits, don?t set them in normal operation. table 8: mac register mapping offset name description default value 0xfc00 cmd command register 0x0000_0201 0xfc04 imr interrupt mask register 0x0000_0000 0xfc08 isr interrupt status register 0x0000_0000 0xfc10 tx_cfg tx configuration register 0x0000_0040 0xfc14 tx_cmd tx command register 0x0000_0000 0xfc18 txbs tx buffer status register 0x0000_0000 0xfc1c phy_ctrl internal phy control register * 0x0000_0000 0xfc20 txdes0 tx descriptor0 register 0x0000_0000 0xfc24 txdes1 tx descriptor1 register 0x0000_0000 0xfc28 txdes2 tx descriptor2 register 0x0000_0000 0xfc2c txdes3 tx descriptor3 register 0x0000_0000 0xfc30 rx_cfg rx configuration register 0x0000_0101 0xfc34 rxcurt rx current pointer register 0x0000_0000 0xfc38 rxbound rx boundary pointer register 0x0000_07ff 0xfc40 mac_cfg0 mac configuration0 register 0x0000_8157 0xfc44 mac_cfg1 mac configuration1 register 0x0000_6000 0xfc48 mac_cfg2 mac configuration2 register 0x0000_0100 0xfc4c mac_cfg3 mac configuration3 register 0x0000_060e 0xfc54 txpaut tx pause time register 0x001f_e000 0xfc58 rxbthd0 rx buffer threshold0 register 0x0000_0300 0xfc5c rxbthd1 rx buffer threshold1 register 0x0000_0600 0xfc60 rxfulthd rx buffer full threshold register 0x0000_0100 0xfc68 misc misc. control register 0x0000_0013 0xfc70 macid0 mac id0 register * 0x0000_0000 0xfc74 macid1 mac id1 register * 0x0000_0000 0xfc78 macid2 mac id2 register * 0x0000_0000 0xfc7c txlen tx length register 0x0000_05fc 0xfc80 rxfilter rx packet filter register 0x0000_0004 0xfc84 mdioctrl mdio control register 0x0000_0000 0xfc88 mdiodp mdio data port register 0x0000_0000 0xfc8c gpio_ctrl gpio control register * 0x0000_0003 0xfc90 rxindicator receive i ndicator register 0x0000_0000 0xfc94 txst tx status register 0x0000_0000 0xfca0 mdclkpat mdc clock pattern register 0x0000_8040 0xfca4 rxchksumcnt rx ip/udp/tcp checksum error counter 0x0000_0000 0xfca8 rxcrcnt rx crc error counter 0x0000_0000 0xfcac txfailcnt tx fail counter 0x0000_0000 0xfcb0 promdpr eeprom data port register 0x0000_0000 0xfcb4 promctrl eeprom control register 0x0000_0000 0xfcb8 maxrxlen max. rx packet length register 0x0000_0600 0xfcc0 hashtab0 hash table0 register * 0x0000_0000 0xfcc4 hashtab1 hash table1 register * 0x0000_0000 0xfcc8 hashtab2 hash table2 register * 0x0000_0000 0xfccc hashtab3 hash table3 register * 0x0000_0000 0xfce0 dogthd0 watch dog timer threshold0 register 0x0000_ffff 0xfce4 dogthd1 watch dog timer threshold1 register 0x0000_0000 0xfcec softrst software reset register 0x0000_0003 *note: it is not affected by software reset
AX88780 18 asix electronics corporation 4.1 cmd--command register offset address = 0xfc00 default = 0x0000_0201 field name type default description 31:16 - r/w all 0?s reserved 15 rxvlan r/w 0 rx vlan indicator driver enables this bit to indicate AX88780 that the recei ved packet will include 4 bytes vlan tag; AX88780 will skip 4 bytes when it calculates the checksum of ip, tcp or udp packet. 1 = enable 0 = disable 14 txvlan r/w 0 tx vlan indicator driver enables this bit to indicate AX88780 that the transmitted packet will include 4 bytes vlan tag; AX88780 will skip 4 bytes when it calculates the checksum of ip, tcp or udp packet. 1 = enable 0 = disable 13:10 - r/w all 0?s reserved 9 rxen r/w 1 rx function enable when this bit is enabled, mac starts to receive packets. 1 = enable 0 = disable 8 txen r/w 0 tx function enable when this bit is enabled, mac could start to transmit packet to ethernet. 1 = enable 0 = disable 7 - r/w 0 reserved 6 intmod r/w 0 interrupt active mode driver sets this bit to indicate AX88780 that the interrupt of system is activated high or low. 1: active high 0: active low 5:1 - r/w all 0?s reserved 0 wakemod r/w 1 wakeup pin polarity driver sets this bit to indicate AX88780 that the polarity of system wake-up signal is activated high or low. 1: active high 0: active low 4.2 imr--interrupt mask register offset address = 0xfc04 default = 0x0000_0000 field name type default description 31:6 - r all 0?s reserved 5 phymask r/w 0 phy interrupt mask when this bit is enabled, an interrupt request from phy set in bit 5 of interrupt status register will make AX88780 to issue an interrupt to host. 1 = enable 0 = disable 4 prim r/w 0 packet recei ved interrupt mask when this bit is enabled, a received interrupt request set in bit 4 of interrupt status register will make AX88780 to issue an interrupt to host. 1 = enable 0 = disable 3 ptim r/w 0 packet transmitted interrupt mask when this bit is enabled, a transmitted in terrupt request set in bit 3 of interrupt status register will make AX88780 issue an interrupt to host.
AX88780 19 asix electronics corporation 1 = enable 0 = disable 2 - r/w 0 reserved 1 dogim r/w 0 watch dog timer interrupt mask when this bit is enabled, a watch dog timer expired interrupt request set in bit1 of interrupt status register will make AX88780 to issue an interrupt to host 1 = enable 0 = disable 0 rxfulim r/w 0 rx buffer full interrupt mask when this bit is enabled, a rx buffer full interrupt request set in bit 0 of interrupt status register will make AX88780 to issue an interrupt to host. 1 = enable 0 = disable 4.3 isr--interrupt status register offset address = 0xfc08 default = 0x0000_0000 field name type default description 31:6 - r all 0?s reserved 5 phyig r/w 0 phy interrupt generation if this bit is set to ?1? it means there is an interrupt request from phy. mac will forward this interrupt to system. meantime driver should poll phy and adopt proper procedure. write ?1? to this bit to clear this request status. 1 = have interrupt request 0 = no interrupt request 4 rpig r/w 0 receive packet interrupt generation if this bit is set to ?1? it means mac r eceives a packet or (packets) from cable. the packet is kept in rx buffer. write ?1? to this bit to clear this request status. 1 = have received packet 0 = no received packet 3 ftpi r/w 0 finish transmitting packet interrupt if this bit is set to ?1? it means mac had transmitted packet to cable. write ?1? to this bit to clear this request status. 1 = finish transmitting 0 = none 2 - r/w 0 reserved 1 wdtei r/w 0 watch dog timer expired interrupt if this bit is set to ?1? it means the watch dog timer is expired. AX88780 will issue an interrupt to host. write ?1? to this bit to clear this request status. the expired duration can refer to dogthd0 and dogthd1 registers. 1 = timer expired happens 0 = none 0 rxfuli r/w 0 rx buffer full interrupt if this bit is set to ?1? it means rx buffer is full and no more packets will be received until packets are read out. write ?1? to this bit to clear this request status. 1 = rx buffer full 0 = none
AX88780 20 asix electronics corporation 4.4 tx_cfg--tx configuration register offset address = 0xfc10 default = 0x0000_0040 field name type default description 31:7 - r all 0?s reserved 6 txcrcap r/w 1 txcrc auto-append when this bit is enabled, AX88780 will append crc to the transmitted packet in fcs field. 1 = enable 0 = disable 5 - r/w 0 reserved. 4 txchksum r/w 0 tx checksum generation when this bit is enabled, AX88780 will append checksum to the transmitted packet that is ip or tcp or udp packet. 1 = enable 0 = disable 3:2 - r 00 reserved 1:0 txds r 00 tx description status AX88780 reports which descriptor is transmitted now default: 00 4.5 tx_cmd--tx command register offset address = 0xfc14 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 hwi r/w 0 host writes indication before host begins to send a packet to tx buffer, this bit should be set. at the end of host writes the packet, this bit should be cleared. 1 = start writing 0 = end writing 14:13 txdp r/w 00 tx descriptor pointer to specify which tx descriptor to be written. 12 - r/w 0 reserved 11:0 datalen r/w all 0?s byte count. data length is written to transmitted buffer. 4.6 txbs--tx buffer status register offset address = 0xfc18 default = 0x0000_0000 field name type default description 31:4 - r all 0?s reserved 8 intxds r 0 internal tx descriptor status. this bit reports the tx descriptor status. when there is data to be transmitted, this bit will be set to ?1? otherwise it will be ?0? 1 = have data in tx buffer 0 = all data are transmitted to cable 7:6 - r 00 reserved 5:4 txduse r 00 tx descriptor in transmitting these status bits indicate which descriptor is transmitting now. 00: descriptor 0 in transmitting 01: descriptor 1 in transmitting 10: descriptor 2 in transmitting 11: descriptor 3 in transmitting 3 txd3o r/w 0 tx descriptor 3 occupied driver set this bit to ?1? to indicate that it had used tx descriptor3. when the
AX88780 21 asix electronics corporation transmission is finished, AX88780 will auto-clear this bit. 2 txd2o r/w 0 tx descriptor 2 occupied driver set this bit to ?1? to indicate that it had used tx descriptor2. when the transmission is finished, AX88780 will auto-clear this bit. 1 txd1o r/w 0 tx descriptor 1 occupied driver set this bit to ?1? to indicate that it had used tx descriptor1. when the transmission is finished, AX88780 will auto-clear this bit. 0 txd0o r/w 0 tx descriptor 0 occupied driver set this bit to ?1? to indicate that it had used tx descriptor0. when the transmission is finished, AX88780 will auto-clear this bit. 4.7 phy_ctrl-- internal phy control register offset address = 0xfc1c default = 0x0000_0000 field name type default description 31:13 - r all 0?s reserved 12 spd_gpio1 r/w 0 speed led or gpio1 when this bit is enabled, pin54 is as speed indicator, otherwise it is as gpio1 function and controlled by gpio_ctrl register. 1= enable 0= disable 11 lnk_gpio0 r/w 0 link led or gpio0 when this bit is enabled, pin55 is as link/traffic indicator, otherwise it is as gpio0 function and controlled by gpio_ctrl register. 1 = enable 0 = disable 10 ful_eecs r/w 0 eecs pin as full-duplex led when this bit is enabled, eecs pin will be as full-duplex indicator and eedi pin will be as collision indicator. 1 = enable 0 = disable 9 pwdn r/w 0 power down phy when this bit is enabled, AX88780 will turn off (disable) internal phy. 1 = enable 0 = disable 8 phy_en r/w 0 phy selection when this bit is enabled, AX88780 will select internal phy, otherwise it will select external phy. 1 = enable 0 = disable 7 - r 0 reserved 6:4 phyopmode r/w 000 internal 10/100m phy operation mode driver can set these bits to cont rol internal phy operation mode. 000 = auto-negotiation enable with all capability 001 = auto-negotiation with 100base-tx fdx/hdx ability 010 = auto-negotiation with 10base-t fdx/hdx ability 011 = reserved 100 = manual selection of 100base-tx fdx 101 = manual selection of 100base-tx hdx 110 = manual selection of 10base-t fdx 111 = manual selection of 10base-t hdx 3:1 - r 000 reserved 0 - r/w 0 reserved, must to be 0
AX88780 22 asix electronics corporation 4.8 txdes0--tx descriptor0 register offset address = 0xfc20 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 txd0_en r/w 0 transmit tx descriptor 0 if this bit is enabled, mac will begin to transmit data that are stored in tx buffer. in former, data had been written to tx descriptor0. this bit will be cleared by hardware when ma c finished the transmission. 1= enable 0= disable 14:13 - r 00 reserved 12:0 txd0_len r/w all 0?s tx pa cket length (unit: byte) driver set this field to indicate AX88780 how many bytes will be transmitted. 4.9 txdes1--tx descriptor1 register offset address = 0xfc24 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 txd1_en r/w 0 transmit tx descriptor 1 if this bit is enabled, mac will begin to transmit data that are stored in tx b uffer. in former, data had been written to tx descriptor1. this bit will be cleared by hardware when ma c finished the transmission. 1= enable 0= disable 14:13 - r 00 reserved 12:0 txd1_len r/w all 0?s tx packet length (unit: byte) driver set this field to indicate AX88780 how many bytes will be transmitted. 4.10 txdes2--tx descriptor2 register offset address = 0xfc28 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 txd2_en r/w 0 transmit tx descriptor 2 if this bit is enabled, mac will begin to transmit data that are stored in tx b uffer. in former, data had been written to tx descriptor2. this bit will be cleared by hardware when ma c finished the transmission. 1= enable 0= disable 14:13 - r 00 reserved 12:0 txd2_len r/w all 0?s tx packet length (unit: byte) driver set this field to indicate AX88780 how many bytes will be transmitted.
AX88780 23 asix electronics corporation 4.11 txdes3--tx descriptor3 register offset address = 0xfc2c default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 txd3_en r/w 0 transmit tx descriptor 3 if this bit is enabled, mac will begin to transmit data that are stored in tx b uffer. in former, data had been written to tx descriptor3. this bit will be cleared by hardware when ma c finished the transmission. 1= enable 0= disable 14:13 - r 00 reserved 12:0 txd3_len r/w all 0?s tx packet length (unit: byte) driver set this field to indicate AX88780 how many bytes will be transmitted. 4.12 rx_cfg--rx configuration register offset address = 0xfc30h default = 0x0000_0101 field name type default description 31:9 - r all 0?s reserved 8 rxbme r/w 1 rx buffer monitor enable when this bit is enable, mac will mon itor the status of the receive buffer. 1 = enable 0 = disable 7:5 - r/w 000 reserved. 4 rxchksum r/w 0 rx pa cket tcp/ip checksum when this bit is set, AX88780 will check the ch ecksum of the received packet that is ip, tcp or udp packet. if there is checksum error, AX88780 will drop the packet and rxchksumcnt counter will add 1. 1 = enable 0 = disable 3:1 - r/w 000 reserved 0 rxbufpro r/w 1 rx buffer protection when this bit is enabled, mac will protect the rx buffer to avoid overrun. for normal operation, this bit should be enabled in initial stage. 1= enable 0= disable 4.13 rxcurt--rx current pointer register offset address = 0xfc34 default = 0x0000_0000 field name type default description 31:11 - r all 0?s reserved 10:0 rxcurptr r/w all 0?s rx line current pointer. point to the last line that will be wr itten by hardware. the unit of line is 16 bytes. mac will maintain this register.
AX88780 24 asix electronics corporation 4.14 rxbound--rx boundary pointer register offset address = 0xfc38 default = 0x0000_07ff field name type default description 31:11 - r all 0?s reserved 10:0 rxbunptr r/w 0x7ff rx line boundary pointer. point to the last line that has been read by driver. the unit of line is 16 bytes. when driver finished read ing packet from rx buffer, it must update this field. 4.15 mac_cfg0--mac configuration0 register offset address = 0xfc40 default = 0x0000_8157 field name type default description 31:16 - r all 0?s reserved 15 speed100 r/w 1 line speed mode when this bit is enabled, the mac of AX88780 will operate in 100m speed, otherwise it will operate in 10m speed. the line speed must co-operate with setting of phy. 1 = 100m 0 = 10m 14 - r/w 0 reserved, this bit must set to 0 for normal operation 13 - r/w 0 reserved, this bit must set to 0 for normal operation. 12 rxflow r/w 0 rx flow control if this bit and bit8 of rx_cfg are enabled, mac will perform flow control and send pause on/off frame when the available space of receive buffer is less than the value of rxbthd0. 1 = enable 0 = disable 11 - r/w 0 reserved, this bit must set to 0 for normal operation. 10:4 ipgt r/w 0x15 inter packet gap time: (ipg) this field defines the back-to-back transmit packet gap for 10/100m only. 3:0 - r/w 0x7 reserved, keep the default value for normal operation. 4.16 mac_cfg1--mac configuration1 register offset address = 0xfc44 default = 0x0000_6000 field name type default description 31:15 - r all 0?s reserved 14 pusrule r/w 1 pause frame check rule when this bit is set, AX88780 accept s pause frame that da can be any value. 1 = don?t check da field. 0 = check da is equal to ?01 80 c2 00 00 01? 13 crcchk r/w 1 check crc of received packet. when this bit is enabled, AX88780 will drop any crc error packet. 1 = enable 0 = disable 12:7 - r/w all 0?s reserved, keep all bits in ?0? for normal operation. 6 duplex r/w 0 duplex mode. 1 = full-duplex mode 0 = half-duplex mode 5 txflw_en r/w 0 tx flow enable when this bit is enabled, mac will block the transmitted operation when it captures pause frame from ethernet. the re-transmission will be activated
AX88780 25 asix electronics corporation until the waiting time is expired. 1 = enable 0 = disable 4:1 - r/w 0000 reserved, must set to ?0s? for normal operation 0 - r/w 0 reserved, must set to ?0s? for normal operation 4.17 mac_cfg2--mac configuration2 register offset address = 0xfc48 default = 0x0000_0100 field name type default description 15:8 - r/w 0x01 reserved, keep this field in default value for normal operation. 7:2 jamlt r/w 000000 define jam limit for backpressure collision account. n ormally set this field at 0x19. it can avoid hub port going to partition state due to too many collisions. AX88780 will skip one frame collision backpressure when collision counter equal to jamlt. the collision count will be reset to zero when every transmit frame with no collision or receive a frame with no backpressure collision. 1:0 - r/w 00 reserved, must set to ?00? for normal operation 4.18 mac_cfg3--mac configuration3 register offset address = 0xfc4c default = 0x0000_060e field name type default description 15 noabort r/w 0 no abort when this bit is enabled, mac will ke ep retry transmit current frame even excessive collision otherwise it will abort current transmission due to excessive collision. 1 = enable 0 = disable 13:7 ipgr1 r/w 0001100 inter-frame gap segment1 6:0 ipgr2 r/w 0001110 inter-frame gap segment2 4.19 txpaut--tx pause time register offset address= 0xfc54 default = 0x001f_e000 field name type default description 31:23 - r reserved 22:0 txpval r/w 0x1f_e000 tx pause time out it is used to re-transmit a pause-on frame when pause timer expired and receive buffer still not enough. in 32-bit mode, this field should be set to 0x7f_8000. in 16-bit mode, this field should be set to 0xffff at 10/100mbps modes. (note: the bit 16 ~ 22 of this field are invalid in 16-bit mode.) 4.20 rxbthd0--rx buffer threshold0 register offset address= 0xfc58 default = 0x0000_0300 field name type default description 31:11 - r all 0?s reserved 10:0 rxlowb r/w 0x300 rx remainder capacity low-bound this field defines as the remainder capacity of rx buffer for pause operation. if the flow control (bit12 of maccfg0) is enabled, mac will send pause frame when the available sp ace of receive buffer is less than this value. the unit is 16-byte.
AX88780 26 asix electronics corporation 4.21 rxbthd1--rx buffer threshold1 register offset address= 0xfc5c default = 0x0000_0600 field name type default description 31:11 - r all 0?s reserved 10:0 rxhighb r/w 0x600 rx remainder capacity upper-bound this field defines as upper bound of remainder size of rx buffer for pause operation. if the flow control is enabled, mac will stop to send pause frame until the available space of receive buffer is more than this value. the unit is 16-byte. 4.22 rxfulthd--rx buffer full threshold register offset address= 0xfc60 default = 0x0000_0100 field name type default description 31:11 - r all 0?s reserved 10:0 rxfulb r/w 0x100 rx full threshold this field defines the least capacity of rx buffer. AX88780 will cause rx full if it remains capacity less than this value. the unit is 16-byte. 4.23 misc?misc. control register offset address= 0xfc68 default = 0x0000_0013 field name type default description 31:6 - r all 0?s reserved 5 wake_lnk r/w 0 wake-up by link-up function if this bit is enabled, mac will drive wakeup pin whenever there is link-up occurrence. the polarity of wakeup pin is according to bit0 of cmd register. 1= enable 0= disable 4 wake_mag r/w 1 wake-up by magic packet if this bit is enabled, mac will driv e wakeup pin whenever there is magic p acket detected by hardware. the polarity of wakeup pin is according to bit0 of cmd register. 1= enable wake-up by magic packet 0 = disable 3:2 - r/w 00 reserved 1 srst_phy r/w 1 software reset internal phy driver set this bit to ?0? to reset internal phy. the reset duration is depended on whenever this bit is de-asserted by deriver. 1 = in normal operation 0 = in reset status 0 srst_mac r/w 1 software reset mac driver set this bit to ?0? to reset mac. the reset duration is depended on whenever this bit is de-asserted by deriver. after power-on, driver must activate software reset mac once before initial other registers. 1 = in normal operation 0 = in reset status
AX88780 27 asix electronics corporation 4.24 macid0--mac id0 register offset address = 0xfc70h default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved. 15:0 mid15_0 r/w 0x0000 mac id address [15:0]. this field defines lower address bit15 to bit0 of mac. the macid0, macid1 and macid2 comb ine into 48- b it mac address. the mac address format is [47:0] = {macid2[15:0], macid1[15:0], macid0[15:0]}. if the eeprom is attached, this field will be auto-loaded from eeprom after hardware reset. 4.25 macid1--mac id1 register offset address = 0xfc74 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved. 15:0 mid31_16 r/w 0x0000 mac id address [31:16]. 4.26 macid2--mac id2 register offset address = 0xfc78h default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved. 15:0 mid47_32 r/w 0x0000 mac id address [47:32]. 4.27 txlen--tx length register offset address = 0xfc7c default = 0x0000_05fc field name type default description 31:11 - r all 0?s reserved 10:0 maxtxlen r/w 0x5fc max tx packet size this field defines the maximum raw pack et size in transmittance. it is not included 4 bytes fcs. 4.28 rxfilter--rx packet filter register offset address = 0xfc80 default = 0x0000_0004 field name type default description 31:6 - r all 0?s reserved 5 goodcrc r/w 0 good crc enable when this bit is enabled, AX88780 will receive any packet of good crc. 1 = enable 0 = disable 4 multi_hash r/w 0 receive multicast packet by lookup hash table. when this is enabled, AX88780 will receive multicast packet by the hash mapping function. it will refer to hastab0, hashtab1, hashtab2 and hashtab3 to look up the table. 1 = enable 0 = disable 3 broadcast r/w 0 receive broadcast packet when this bit is enabled, AX88780 will receive the broadcast packet 1 = enable
AX88780 28 asix electronics corporation 0 = disable 2 unicast r/w 1 receive directed packet. if this bit is enabled, AX88780 will compare the destination address field of received packet with the address of mac (r efer to macid0, macid1, macid2). when it is matched and good crc, the packet will be passed to driver. otherwise it will be dropped. 1 = enable 0 = disable 1 multicast r/w 0 receive all multicast packets. if this bit is enabled, any multicast packet (good crc) will b e received and passed to driver. 1 = enable 0 = disable 0 rxany r/w 0 receive anything. if this bit is enabled, any packet whether it is good or fail will be received and passed to driver. 1 = enable 0 = disable 4.29 mdioctrl--mdio control register offset address = 0xfc84 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 wten r/w 0 write enable. driver enables this bit to issue a write cycle to phy, it will be cleared when finished the write cycle 1 = enable 0 = disable 14 rden r/w 0 read enable. driver enables this bit to issue a read cy cle to phy. this bit will be cleared when finished the read cycle 1 = enable 0 = disable 12:8 phycridx r/w 00000 phy register index if driver wants to access phy, set this field to define the internal register index of phy. 7:5 - r 000 reserved 4:0 phyid r/w 00000 phy id if driver wants to access phy, set this fiel d to define the address (id) of phy. the address of internal phy is fixed to 0x10 4.30 mdiodp--mdio data port register offset address = 0xfc88 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 mdport r/w all 0?s phy data port to or from internal phy data is put in this field.
AX88780 29 asix electronics corporation 4.31 gpio_ctrl--gpio control register offset address = 0xfc8c default = 0x0000_0003 field name type default description 31:10 - r all 0?s reserved 9 gpio1s r/w 0 gpio1 status this bit stands for the pin status of gpio1 when it is set to input mode. 1 = high state 0 = low state 8 gpio0s r/w 0 gpio0 status this bit stands for the pin status of gpio0 when it is set to input mode. 1 = high state 0 = low state 7:2 - r all 0?s reserved 1 gpio1dir r/w 1 gpio1 mode direction this field defines the direction of gpio1 pin. 1 = input mode 0 = output mode 0 gpio0dir r/w 1 gpio0 mode direction this field defines the direction of gpio pin. 1 = input mode 0 = output mode note: for output mode, software must firstly set the bit0 or bit1 to output mode then set bit8 or bit9. 4.32 rxindicator--receive indicator register offset address= 0xfc90 default = 0x0000_0000 field name type default description 31:1 - r all 0?s reserved 0 rxstart r/w 0 receive start driver set this bit to st art or end receive operation from rx buffer of mac. 1= start read rx buffer 0= end read rx buffer 4.33 txst--tx status register offset address = 0xfc94 default = 0x0000_0000 field name type default description 31:4 - r all 0?s reserved 3 txd3fail r 0 tx descriptor3 transmit fail when this bit is set 1, it means mac fails in transmission of descriptor 3. this bit will be self-cleared when driver reads txst register. 2 txd2fail r 0 tx descriptor2 transmit fail when this bit is set 1, it means mac fails in transmission of descriptor 2. this bit will be self-cleared when driver reads txst register. 1 txd1fail r 0 tx descriptor1 transmit fail when this bit is set 1, it means mac fails in transmission of descriptor 1. this bit will be self-cleared when driver reads txst register. 0 txd0fail r 0 tx descriptor0 transmit fail when this bit is set 1, it means mac fails in transmission of descriptor 0. this bit will be self-cleared when driver reads txst register.
AX88780 30 asix electronics corporation 4.34 mdclkpat--mdc clock pattern register offset address = 0xfca0 default = 0x0000_8040 field name type default description 31:16 - r all 0?s reserved 15:8 - r/w 0x80 reserved, must set to 0x80 for normal operation 7:0 mdcpat r/w 0x40 mdc clock divide factor this field defines the divide factor of host clock. AX88780 will refer to this field and generate a low speed clock to phy. 4.35 rxchksumcnt--rx ip/udp/tcp checksum error counter offset address = 0xfca4 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 rxchkercnt r/w all 0?s rx checksum error counter if the rxchksum field of rx_cfg regist er is set to ?1?, mac will check the checksum of ip, tcp or udp packet. whenever there is checksum error detected, this field will be added one. the value will be rounded back to 0x0000 if it exceeds 0xffff. 4.36 rxcrcnt--rx crc error counter offset address = 0xfca8 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 rxcrccnt r/w all 0?s rx crc32 error counter mac checks the received packet. if there is a crc error detect, this field will be added one. the value will be rounde d back to 0x0000 if it exceeds 0xffff. 4.37 txfailcnt--tx fail counter offset address = 0xfcac default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 txfilcnt r/w all 0?s tx fail counter this field records the number of transm itted error for tx packet. the value will be rounded back to 0x0000 if it exceeds 0xffff. 4.38 promdpr--eeprom data port register offset address = 0xfcb0h default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 promdp r/w all 0?s eeprom data port the data to or from eeprom is set in this field.
AX88780 31 asix electronics corporation 4.39 promctrl--eeprom control register offset address= 0xfcb4 default = 0x0000_0000 field name type default description 31:15 - r all 0?s reserved 14:12 rom_cmd r/w 000 eeprom command code. driver set this field to represent what type command will be send to eeprom device. 110 = read command 111 = erase command 101 = write command 11 rom_wt r/w 0 write eeprom set to ?1? to write eeprom, it will be cleared when mac finished the write operation. 10 rom_rd r/w 0 read eeprom set to ?1? to read eeprom, it will be cleared when mac finished the read operation. driver can read promdpr register to get the returned data. 9 rom_rld r/w 0 reload eeprom set to ?1? to re-load eeprom, this bit will be cleared when mac finished loading operation. 8 - r 0 reserved 7:0 rom_addr r/w 0x00 eeprom address set this field to define the address for serial eeprom access. (only support 16-bit data access, 93c56 type) 4.40 maxrxlen--max. rx packet length register offset address= 0xfcb8 default = 0x0000_0600 field name type default description 31:11 - r all 0?s reserved 10:0 rxlen r/w 0x600 max rx packet length this field defines the max length of recei ved packet. it doesn?t include 4-byte crc. 4.41 hashtab0--hash table0 register offset address = 0xfcc0 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 htab0 r/w 0x0000 hash table: bit15~bit0 driver sets hashtab0, hashtab1, hashtab2 and hashtab3 to define 64-bit hash table. AX88780 will refer this table to check multicast packet if multicast filter is enabled for rx. wh en AX88780 receives a packet then it extracts the destination address (da). th e da is calculated by crc32 algorithm. after the operation, AX88780 will grab th e msb[31:27] of result as hash table index. the range of index is from 0 to 63. for example, the hash table is composite as {hashtab3[15:0], hashtab2[15:0], hashtab1[15:0], hashtab0[15:0]}. if AX88780 detects the msb[31:27] = 26 of crc32 of da for someone multicast packet, and driver set ?1? to hashtab1[10], then the multicast packet will received by AX88780.
AX88780 32 asix electronics corporation 4.42 hashtab1--hash table1 register offset address = 0xfcc4 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 htab1 r/w 0x0000 hash table: bit31~bit16 4.43 hashtab2--hash table2 register offset address = 0xfcc8 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 htab2 r/w 0x0000 hash table: bit47~bit32 4.44 hashtab3--hash table3 register offset address = 0xfccc default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15:0 htab3 r/w 0x0000 hash table: bit63 ~ bit48 4.45 dogthd0?watch dog timer threshold0 register offset address = 0xfce0 default = 0x0000_ffff field name type default description 31:16 - r all 0?s reserved 15:0 dogth0 r/w 0xffff watch dog timer low word this register and dogthd1[11:0] are defined to an expired threshold for internal watchdog counter. the thres hold {[dogthd1, dogthd0] is a 28-bit value. to multiply 28-bit value with one- cycle period of a host clock is the expired duration. if the dogen is set to ?1? and wdtei of isr is set, then AX88780 will periodically generate interrupt whenever the counter reaches to the threshold. 4.46 dogthd1?watch dog timer threshold1 register offset address = 0xfce4 default = 0x0000_0000 field name type default description 31:16 - r all 0?s reserved 15 dogen r/w 0 dog timer enable 1 = enable internal dog timer 14:12 - r/w all 0s reserved 11:0 dogth1 r/w 0x000 dog timer high byte. this filed and dogthd0[15:0] combine to a 28-bit register.
AX88780 33 asix electronics corporation 4.47 softrst ? software reset register offset address = 0xfcec default = 0x0000_0003 field name type default description 31:2 - r all 0?s reserved 1 rst_phy r/w 1 reset internal phy driver set this bit to ?0? to reset internal phy. the reset duration is depended on whenever this bit is de-asserted by driv er. all registers of phy will be clean to default value. 1 = in normal operation 0 = in reset status 0 rst_mac r/w 1 reset mac driver set this bit to ?0? to reset mac. the reset duration is depended on whenever this bit is de-asserted by driver. most registers of mac will be clear to default value. 1 = in normal operation 0 = in reset status
AX88780 34 asix electronics corporation 5.0 phy register AX88780 is built a high performance 10/ 100m phy for cost-effective. driver can access these registers of phy by in-directed mechanism. for write operation, software firstly sets data to mdiodp re gister, then sets index and write enable bit to mdioctrl register. ax 88780 will access phy by internal interface and clear the write enable bit whenever the operation finished. for read operation, driver sets the inde x and read enable bit to mdioctrl register, then polls the read-enable bit. the returned data will be put in mdio dp register whenever the read-enable bit is cleared. table 9 : phy register mapping index name description 0x00 bmcr basic mode control register 0x01 bmsr basic mode status register 0x02 phyidr0 phy identifier 0 register 0x03 phyidr1 phy identifier 1 register 0x04 anar auto-negotiation advertisement register 0x05 anlpar auto-negotiation link partner ability register 0x06 aner auto-negotiation expansion register t he following abbreviations apply to below sections for detained register description. access type r = read only rw= read/write attribute: ll = latch low lh = latch high sc = self-clearing ps = value is permanently set x = don?t care 5.1 bmcr--basic mode control register index = 0x00 field name type default description 15 phyrst r/w 0, sc soft reset: 1 = software reset phy, this bit will be cleared when reset finish. 0 = normal operation 14 loopback r/w 0 loop back operation: 1 = loop back enable 0 = loop back disable 13 spdsel r/w 1 speed selection: 1 = 100mb/s 0 = 10mb/s 12 autoneg_en rw 1 auto-negotiation enable: 1 = enable, bit8 and bit13 will be ignored when this bit is enabled. 0 = disable, bit8 and bit13 of this register determine the link speed and mode. 11 phypwdn r/w 0 power down: 1 = power-down enable 0 = normal operation 10 - r 0 reserved 9 autoneg_rs r/w 0 auto-negotiation restart: 1=restart auto-negotiation, this bit will be cleared when finish negotiation. 0=normal operation 8 dplx r/w 1 duplex mode:
AX88780 35 asix electronics corporation 1=full-duplex operation 0= normal operation 7 coltst r/w 0 collision test: 1=enable collision test 0= normal operation 6:0 - r x reserved 5.2 bmsr--basic mode status register index = 0x01 field name type default description 15 100bcap r 0, ps 100base-t4 capability 0 = AX88780 is not able to execute 100 base-t4 mode. 14 100bful r 1, ps 100base-tx full-duplex capability: 1= AX88780 is able to perform in 100base-tx full-duplex mode. 13 100bhaf r 1, ps 100base-tx half-duplex capability: 1 = AX88780 is able to perform in 100base-tx half-duplex mode. 12 10bful r 1, ps 10base-t full-duplex capability: 1 = AX88780 is able to perform in 10base-t full-duplex mode. 11 10bhaf r 1, ps 10base-t half-duplex capability: 1 = AX88780 is able to perform in 10base-t half-duplex mode. 10:7 - r all 0?s reserved, default 4?b0000 6 mfps r 0, ps management frame preamble suppression: 0 = AX88780 will not accept management frames with preamble suppressed. 5 autonest r 0 auto negotiation completion: 1 = auto-negotiation process is complete. 0 = auto-negotiation process is not completed 4 rfst rc 0, lh remote fault status: 1 = the link partner signals a far-end fault, read to clear. 0 = remote fault condition is not detected 3 autocfg r 1, ps auto configuration ability: 1 = AX88780 is able to perform auto-negotiation 2 lnkst r 0, ll link status: 1= valid link is established, (100mb/s or 10mb/s operation) 0= valid link is not established 1 jabdet r 0, lh jabber detection: 1= jabber condition is detected. 0 = jabber condition is not detected 0 extcap r 1, ps extended capability: 1= extended register capable 0= basic register capability only. 5.3 phyidr0--phy identifier 0 register index = 0x02 field name type default description 15:0 ouimsb r 0x003b ps oui most significant bits. bits 3 to 18 of the oui are mapped to bits 15 to 0 of this register respectively. the most significant two bits of the oui are ignored
AX88780 36 asix electronics corporation 5.4 phyidr1--phy identifier 1 register index = 0x03 field name type default description 15:10 ouilsb r 000110 oui lease significant bits. 9:4 manmode r 000011 manufacture?s mode number 3:0 recnum r 0011 revision number 0001 for version 2 0011 for version 3 default 0x1833 ps 5.5 anar--auto-negotiation advertisement register index = 0x04 field name type default description 15 nxtp r 0, ps next page indication: not support 14 - r 0 reserved 13 - r 0 remote fault: not support fault condition detected. 12:11 - r x reserved 10 pf r/w 0 pause function: AX88780 does not support this function in phy layer. the pause function will support with mac operation. 9 100bsup r 0, ps 100base-t4 support: not support 8 100bfulsup r/w 1 100base-tx full-duplex support: 1=enable 100base-tx full duplex 0=disable 100base-tx full-duplex 7 100bhafsup r/w 1 100base-tx half-duplex support: 1=enable 100base-tx half-duplex 0=disable 100base-tx half-duplex. 6 10bfulsup r/w 1 10base-t full-duplex support: 1=enable 10base-t full-duplex 0=disable 10base-t full duplex. 5 10bhafsup r/w 1 10base-t half-duplex support: 1=enable 10base-t half-duplex 0=disable 10base-t half-duplex. 4:0 prosel r/w 00001 protocol selection bits: AX88780 support ieee 802.3u csma/cd. 5.6 anlpar--auto-negotiation li nk partner ability register index = 0x05 field name type default description 15 pnrnxt r 0 next page indication: 1= link partner is next page enabled. 0= link partner is not next page enabled 14 pnrack r 0 acknowledgement: 1= link partner ability for reception of data word is acknowledged 0= link partner ability for reception of data word is not acknowledged. 13 pnrrf r 0 remote fault: (from link partner view) 1= remote fault is indicated by link partner. 0= remote fault is not indicated by link partner. 12:11 - r 00 reserved 10 pnrpaus r 0 pause: 1= pause operation is supported by link partner.
AX88780 37 asix electronics corporation 0= pause operation is not support by link partner. 9 pnr100b r 0 100base-t4 support: 1 = 100base-t4 is supported by link partner. 0 = 100base-t4 is not supported by link partner. 8 pnr100bful r 0 100base-tx full-duplex support: 1 = 100base-t full-duplex is supported by link partner. 0 = 100base-tx full-duplex is not supported by link partner. 7 pnr100bhaf r 0 100base-tx half-duplex support: 1 = 100base-tx half-duplex is supported by link partner. 0 = 100base-tx half-duplex is not supported by link partner. 6 pnr10bful r 0 10base-t full-duplex support: 1 = 10base-t full-duplex is supported by link partner. 0 = 10base-t full-duplex is not supported by link partner. 5 pnr10bhaf r 0 10base-t half-duplex support: 1 = 10base-t half-duplex is supported by link partner. 0 = 10base-t half-duplex is not supported by link partner. 4:0 pnrprosel r 00000 protocol selection bits: link partner?s binary encoded protocol selector. 5.7 aner--auto-negotiation expansion register index = 0x06 field name type default description 15:5 - r all 0?s reserved, 4 pardetf r 0, lh parallel detection fault: 1 = fault is detected via parallel detection function 0 = fault is not detected 3 lnkpnrnxt r 0 link partner next page enable: 1 = link partner is next page enabled 0 = link partner is not next page enabled. 2 phynxtpg r 0, ps phy next page enable: 1 = phy is next page enabled 0 = phy is not next page enabled. 1 nprec r 0, lh new page reception: 1 = new page is received 0 = new page is not received. 0 lnkpnran r 0 link partner auto-negotiation enable: 1 = auto-negotiation is supported by link partner, 0 = auto-negotiation is not supported by link partner.
AX88780 38 asix electronics corporation 6.0 electrical specification and timings 6.1 dc characteristics 6.1.1 absolute maximum ratings symbol description rating units t stg storage temperature -40 to 150 c vcc3 power supply of 3.3v -0.3 to vcc3 + 0.3 v vcc2 power supply of 2.5v -0.3 to vcc2 + 0.3 v v i3 input voltage of 3.3v io with 5v tolerance -0.3 to 5.5 v v i2 input voltage of 2.5v io with 3.3v tolerance -0.3 to 3.9 v note: stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended pe riod, adversely affect device life and reliability. 6.1.2 general operation conditions symbol description min typ max units tj junction temperature 0 - 115 c vcc2 supply voltage of 2.5v 2.25 2.5 2.75 v vcc3 supply voltage of 3.3v 3.0 3.3 3.6 v v i3 input voltage of 3.3v io with 5v tolerance 0 3.3 5.25 v v i2 input voltage of 2.5v io with 3.3v tolerance 0 2.5 3.6 v 6.1.3 leakage curren t and capacitance symbol description min typ max units i in input leakage current -10 1 +10 a i oz tri-state leakage current -10 1 +10 a c out output capacitance - 3.1 - pf c bid bi-directional buffer capacitance - 3.1 - pf 6.1.4 dc characteristics of 2.5v io pins symbol description min typ max units vcc2 power supply of 2.5v io 2.25 2.5 2.75 v vil input low voltage - - 0.7 v vih input high voltage 1.7 - - v vol output low voltage - - 0.4 v voh output high voltage 1.85 v rpu input pull-up resistance 40 75 190 k rpd input pull-down resistance 40 75 190 k
AX88780 39 asix electronics corporation 6.1.5 dc characteristics of 3.3v io pins symbol description min typ max units vcc3 power supply of 3.3v io 3.0 3.3 3.6 v vil input low voltage - - 0.8 v vih input high voltage 2.0 - - v vol output low voltage - - 0.4 v voh output high voltage 2.4 v rpu input pull-up resistance 40 75 190 k rpd input pull-down resistance 40 75 190 k 6.1.6 transmission characteristics symbol description conditi ons min. typ. max. units vpp peak-to-peak differential output voltage 10base-t mode 4.5 5 5.5 v 2xvtxa peak-to-peak differential output voltage, 2xvtxa 100base-tx 1.9 2 2.1 v t r /t f signal rising/falling time 100base-tx 3 4 5 ns t jit output jitter 100base-tx 1.4 ns vtxov overshoot 100base-tx 5 % 6.1.7 reception ch aracteristics symbol description condition s min. typ. max. units r imp reception impedance 5 k vsqu differential squelch voltage 10base-tx 300 400 500 mv vcom common mode input voltage 1.2 1.6 2 v l free max error-free cable length 100 meter figure 6: transmit waveform specification 0v tr 10% 90% +vtxon +vtxa
AX88780 40 asix electronics corporation 6.1.8 power consumption device only measurement bases on 100mhz frequency of hclk and turn on internal regulator at 25 o c temperature. item symbol power-on with cable removed operation at 10base-t operation at 100base-t phy power down stand-by current (hclk is off) units 1 vcc3 (io) 1.6 5.4 6.4 1.6 0.061 ma 2 vcc3r 103 86 97.5 64 1.5 ma note: the current of vcc3r in cludes vcc2 core current. device and system components it is a total of ethernet connectivity solution, which in cludes external component supporting the AX88780. the brief connection is shown as below. measurement bases on 100mhz frequency of hclk and turn on internal regulator at 25 o c temperature. item test conditions total power units 1 10base-t operation (**internal phy sinks 140 ma) 619 mw 2 100base-t operation (**internal phy sinks 100 ma) 469 mw 3 cable unplug 654 mw 4 phy power down 315 mw vcc3r AX88780 vcc3 v25out transform er ts6121c 1. enable regulator of a x 88780 2. the 2.5v pow er of ts6121c is from a x 88780 vcc2
AX88780 41 asix electronics corporation 6.1.9 thermal characteristics a. junction to ambient thermal resistance, ja symbol min typ max units ja - 46.3 - o c/w b. junction to case thermal resistance, jc symbol min typ max units jc - 16.2 o c/w 1: note ja , jc defined as below ja = p t t a j ? , jc = p t t c j ? t j : maximum junction temperature t a : ambient or environment temperature t c : the top center of com pound surface temperature p: input power (watts) 6.2 a.c. timing characteristics 6.2.1 host clock reference clock (hclk) description min typ. max units reference frequency 40 -- 100 mhz reference clock duty cycle 40 50 60 % 6.2.2 reset timing symbol description min typ. max units trst reset pulse width 1 - - ms hclk rst_n trst
AX88780 42 asix electronics corporation 6.2.3 host single write timing symbol description min typ. max units tsetup csn, wen to hclk setup timing 2 - - ns tar ha exceed to wen timing 0 hclk tad ha exceed to wen timing 0 hclk tvalid_cycle a valid write cycle timing (synchronous to mcu) 4 - - hclk tvalid_cycle a valid write cycle timing- (asynchronous to mcu) 6 - - hclk hclk csn wen valid address ha[15:1] valid data hd[31:0] tsetup tar tad tvalid_cycle
AX88780 43 asix electronics corporation 6.2.4 host burst write timing symbol description min typ. max units twen valid write cycle timing 6 - - hclk 6.2.5 host single read timing symbol description min typ. max units tac csn/oen access timing (synchronous to mcu) 5 - - hclk tac csn/oen access timing (asynchronous to mcu) 6 hclk tovd oen assert to valid data timing 4 - - hclk tdh valid data hold timing to oen de-asserted 0 ns hclk csn ha[15:1] wen address address + 4 address + 8 twen valid data valid data valid data twen hclk csn/oen valid data valid address ha[15:1] hd[31:0] tac tovd tdh
AX88780 44 asix electronics corporation 6.2.6 host burst read timing symbol description min typ. max units tac valid address access timing 6 hclk tovd oen assert to valid data timing 4 - - hclk tad burst mode address to valid data 4 hclk tdh valid data hold timing to oen de-asserted 0 ns 6.2.7 mii receive timing (100mb/s) symbol description min typ. max units trxclk rxclk clock cycle time* 40 ns tsetup rxd[3:0] rxdv setup time for rxclk 5 - - ns thold rxd[3:0], rxdv hold timing for rxclk 3 - - ns rxd[3:0] rxdv tse tup thold rxc lk trxc lk hclk csn oen valid data (a1) valid data (a2) valid data (a3) address (a1) address + 4 (a2) invalid data address + 8 (a3) tovd tad tad tdh tac tac tac
AX88780 45 asix electronics corporation 6.2.8 mii transmit timing (100mbps) symbol description min typ. max units ttxclk txclk reference clock* 40 - ns tdelay txd[3:0], txen delay timing for txclk - 10 ns tsetup txd[3:0], txen setup time 28 ns thold txd[3:0], txen hold time 5 ns *note: for 10mbps, the typical value of ttxclk shall scale to 400ns 6.2.9 mdio timing symbol description min typ. max units tclk mdc clock timing* 1340 - ns tod mdc falling edge to mdio output delay - 32 ns ts mdio data input setup timing 10 - - ns th mdio data input hold timing 4 - - ns *note: hclk is 100mhz case. txd[3 :0] txen txc lk tde la y ttxc lk tse tup thold mdio (output) mdc tc lk mdio ( inp ut) ts th tod
AX88780 46 asix electronics corporation 6.2.10 serial eeprom timing symbol description min typ. max units tclk eeclk clock timing* 1370 - ns tod eeclk falling edge to ee di output delay - 5 ns ts eedo data input setup timing 6 - - ns th eedo data input hold timing 6 - - ns tscs eecs output valid to eeclk rising edge 650 ns thcs eeclk falling edge to eecs invalid timing 0 ns tlcs minimum eecs low timing - 560 - ns *note: hclk is 100mhz case. eedi (output) eeclk tclk eedo (input) ts th tod eecs tlcs thcs tscs
AX88780 47 asix electronics corporation 7.0 package information b e d hd e he pin 1 a2 a1 l l1 a milimeter symbol min. nom max a1 0.05 0.1 a2 1.35 1.4 1.45 a 1.6 b 0.13 0.18 0.23 d 13.90 14.00 14.10 e 13.90 14.00 14.10 e 0.40 hd 15.85 16.00 16.15 he 15.85 16.00 16.15 l 0.45 0.60 0.75 l1 1.00 0 7
AX88780 48 asix electronics corporation 8.0 ordering information AX88780 l f product name package lqfp f: lead free
AX88780 49 asix electronics corporation appendix a1. 16-bit mode address and data bus a1-1. 16-bit mode and separated address and data bus note: the name of control signal for mcu is demonstrated only. a1-1-1. AX88780 is synchronous to host mcu a1-1-2. AX88780 is asynchronous to host mcu note: for asynchronous mode, system must provide extra osc to output clock to AX88780 csn /c sx /r d o en /w r w en clk hclk a[15:1] ha[15:1] d[15:0] hd[15:0] /intx intn /reset rst_n 3.3v generic m cu AX88780 hd[31:16] linkled n ote: floating led diode csn /c sx /r d o e n /w r w e n hclk a[15:1] ha[15:1] d[15:0] hd[15:0] /intx intn /reset rst_n generic m cu AX88780 hd[31:16] linkled n ote: floating osc 3.3v led diode
AX88780 50 asix electronics corporation a1-2. 16-bit mode multiplexed address and data csn /c s x /r d o e n /w r w e n bclk hclk a d [15:0] ha[15:1] hd[15:0] /in t x in t n /reset rst_n generic m cu AX88780 h d [31:16] ale a ddr[15:1] latch linkled n o te : f lo a tin g 3.3v led diode
AX88780 51 asix electronics corporation appendix a2. 32-bit mode address and data bus a2-1. linear address mode and byte aligned (in synchronous mode) note: for asynchronous mode, system must provide extra osc to output clock to AX88780. please refer to section a1-1-2 for details. a2-2. mcu is double-word boundary and the addressing is dword unit csn /c s x /r d oen /w r wen clk hclk a [15:1] ha[15:1] d[31:0] hd[31:0] /in t x in t n /reset rst_n generic mcu a x 88780 linkled g round led diode csn /c s x /r d oen /w r wen clk hclk a[13:0] h a [15:2] d[31:0] h d [31:0] /in t x in t n /r e s e t rst_n generic m cu a x 88780 linkled g round led diode g round ha1
AX88780 52 asix electronics corporation appendix a3. synchronous and asynchronous timing selection AX88780 can support sy nchronous or asynch ronous access from host mcu. be low information provides some references to select clock frequency of host mcu and AX88780. a3-1. AX88780 is synchronous with host mcu. the timing selection is suitable for both 32-bit and 16-bit mode. frequency access type valid access timing (oen/wen active timing) max 100mhz single or burst min 5 clocks a3-2. AX88780 is asynchronous to host mcu. the timing selection is suitable for both 32-bit and 16-bit mode. frequency access type valid access timing (oen/wen active timing) max 100mhz single or burst min 6 reference clocks (note) note: the reference clock is from osc, and it?s not the output of host mcu. for instance, if AX88780 runs in asynchronous mode and refers a 100mhz clock from osc, whereas mcu runs in 125mhz environment. in such condition, mcu must at least offer 60ns (min 6 reference clock of 100mhz) access timing to AX88780. the 60ns for mcu is almost reached to 8 clocks (125mhz). we recommend that it is needed to extend the access timing of mcu to AX88780.
AX88780 53 asix electronics corporation appendix a4. wake on lan (wol) without driver via magic packet a4-1. wake on lan (wol) without driver AX88780 can support wol without driver exists. in su ch situations, system must offer 3.3v voltage, reference clock and rest signal to AX88780. wh enever AX88780 detects magic pa cket from cable, it will drive wakeup signal to host system. AX88780 defaults in mii mode (after reset before eeprom auto-loaded) and uses external phy. in order to use this function, user must set index 5 of eeprom to 0x0002 to enable the internal phy of AX88780. a4-2. magic packet the magic packet received by AX88780 is shown as following; da + sa + 0x0000 + 0xffffffffffff + (at least repeats 16 times) da + crc32 da = mac address of AX88780 (6 bytes) sa = source address (6 bytes)
AX88780 54 asix electronics corporation revision history revision date comment v1.0 2005/10/4 first edition v1.1 2006/7/28 1. some typo errors corrected between pin diagram and tables. 2. host read/write timing revised in section 5. 3. some bits of registers are updated. 4. add some connections between mcu and AX88780 in appendix. 5. add wake up lan description in appendix. v1.2 2007/3/28 1. correct some information in section 3.9 for 16-bit mode operation. 2 . modify the data access timing informati on in section 6.2.5, 6.2.6, 6.2.10 and appendix a3. 3 . change the default value of phyidr1 register for version 3. 4 . add some information in section 3.11. 5. modify some descriptions in section 1.1, 4.6, 4.17, 4.18, 4.19, 4.23, 4.35~37, 4.41. 6 . rearrange the content of appendix into appendix a1~a4. 7 . change the number format from 16h?xxxx to 0xxxxx for example. v1.3 2007/5/4 1. swap th e xtln and xtlp pin defi nitions in section 2.7. 2 . correct some typo errors of pin type in table 4 and table 6. v1.4 2007/5/18 1. modify max operation frequency of hclk from 125mhz to 100mhz. 2. modify some thermal information in section 6.1.9.
AX88780 55 asix electronics corporation 4f, no.8, hsin ann rd., hsinchu science park, hsinchu, taiwan, r.o.c. tel: +886-3-5799500 fax: +886-3-5799558 email: support@asix.com.tw web: http://www.asix.com.tw

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